PORTLAND, Ore. — IBM Research of Zurich is clearing the way for a “new generation of transistor” circuitry based on semiconducting nanowires whose tiny size imparts extraordinary properties not possible with standard bulk materials. The research lab’s latest innovation, accomplished with Norwegian University of Science and Technology, is a novel technique of mechanically straining gallium arsenide (GA As) nanowires on silicon substrates so that they cannot only be tuned to different colors of the spectrum, but can be switched from being emitters of light to being detectors of light as well.
For several years, IBM Zurich has been researching ways to integrate high-electron-mobility III-V materials like gallium arsenide, indium arsenide (In As,) and indium gallium arsenide (In GA As) onto standard silicon complementary metal-oxide semiconductor (CMOS) chips. As a result, the lab has explored many novel III-V compounds.
“There are different future candidates to replace/complement the silicon transistor. III-V materials, and in particularly In GA As ternary alloys, are especially considered for traditional n-channel transistors, because they have higher electron mobility compared to silicon,” said Giorgio Signorelli, an IBM scientist and an author of its latest paper.
IBM Zurich is also investigating other device architectures, like the Tunneling Field Effect Transistor cast in In GA As and In As alloys. The Tunneling FET achieves extraordinary low-energy operation with which IBM hopes to define a new class of nanowire-based CMOS.
“The same class of nanowire materials can also be used to realize some of the optoelectronic components that are needed for the next generation silicon photonic chips. In other words, III-V nanowires enable high-performance CMOS transistors, low-power Tunnel-FETs, silicon photonics, and new physical phenomena which can have technological impact,” said Signorelli.