The Logic Pirate is an inexpensive yet capable open source logic analyzer. For just 30 bucks it can sample 8 channels, 256K samples per channel, at a blazing (overclocked!) 60 MILLION samples per second! It’s designed to support the SUMP logic analyzer protocol on Jawi’s open source software that works on most platforms.
More than a year ago Ian joined the Amp Hour podcast and discussed his goal to make a highly useful, very accessible logic analyzer for around $30. A few weeks later forum regular m.gritsch contacted us about using his design as a successor to the Logic Shrimp v1.
This type of logic analyzer is drastically different than a FPGA-based device like the Logic Sniffer we designed with the Gadget Factory so many years ago. The Logic Sniffer uses programmable logic to create memory, triggers, clocks, tons of fancy stuff all inside one chip. Data is acquired and stored directly inside the FPGA.
The Logic Pirate (based on the Logic Shrimp, which was based on the closed-source Scan logic) uses serial memory chips to store the samples. These chips have much more storage than a FPGA at a much lower cost, however they’re not as fast and lack the complex trigger logic found in a FPGA-based design. If you want max speed and complex triggers, an FPGA design like the Logic Sniffer is a MUCH better choice.
A sneaky feature exploited by the Logic Pirate is overclocking. The SRAM chips used are rated for 20MHz (20MSPS) maximum. However that rating is at temperature and voltage extremes. In practice, we find that sampling up to 60MHz (60MSPS) is reliable in practice! If you’re willing to push the limits, this is a dirt-cheap, big-samplin’ smoking little logic analyzer.
Continue below to read about the v1 initial design, or see the latest revisions on the documentation wiki.
Here are some of its features:
- 8 channels
- 256 k Samples recording size
- 60 MHz (overclocked) sampling rate (20 MHz and lower non-overclocked)
- No compromise when combining the values above
- Simple configurable edge detection triggers on all inputs (simple OR trigger)
- Configurable ratio of samples from before and after the trigger (rolling sample buffer)
- 5 V tolerant inputs (Low-level voltage < 0.8 V, High-level voltage > 2.0 V)
- About 500 kB/s transfer speed to the PC (256 k Samples take about 0.5 seconds)
- Data capturing can be stopped from the host software anytime
- Cross platform host software for Windows, OS X, and Linux
- DIY-friendly 0603 parts and SOIC packages used on a 2-layer board
- On board 3.3 V regulator can supply up to 400 mA to an external circuit
- Tiny 3cm x 3cm PCB
- Firmware updates via built-in USB boot loader
- Probe cables and acrylic case available from Seeed Studio
- Open source PCB (EAGLE) and firmware files
Some features of the host software:
- Precise measurement by using up to ten free place able cursors
- Automatic period, frequency, and duty cycle measurement
- Displaying channel groups as HEX values and/or as an analog signal
- Analyzers for a large number of protocols: 1-Wire, I2C, JTAG, SPI, UART, etc.
The Logic Pirate uses serial SRAM chips to store the sample data. These chips are rated at 20 MHz. USB communication with the host computer and controlling of the SRAMs is done using a PIC32 microcontroller (MCU) which is rated at 40 MHz.
Overclocking the serial SRAMs
Like CPUs on computer mainboards, the chips on the Logic Pirate can be overclocked. The manufacturer of the chips must be conservative on the specified ratings to ensure that the chips function correctly over the whole temperature range.