The whole counter design is based on the PIC micro-controller 16F876A. The latter includes several peripherals and just a few of them are used in this project. The most important in this project are two internal, hardware counters/timers called TMR0 and TMR1. The TMR0 timer generates very precise interrupts every 100 microseconds (10kHz) from the 20MHz clock/reference. All required timings for the counter timebase are simply integer multiples of this basic period.
The TMR1 is used as a 16-bit (binary) input-signal counter. Its maximum counting frequency is just around 16.7MHz. Therefore, the first four flip-flops of the input-signal-counter chain are added externally as 74Fxxx-logic devices. The first two stages use one of the fastest 74Fxxx-series devices, the 74F50109 dual J/K-flip-flop. Further, the 74F50109 is also specified as metastable-immune and is therefore the ideal component for the counter gate.
A more conventional 74F74 dual D-flip-flop is used in the third and fourth stages. The TTL flip-flops require pull-up resistors to drive the PIC ports RC0, RC1, RC2 and RC3. RC0 is used as a clock input to the TMR1 at the same time. Replacing the 74F74 with a 74ACT74 could save some current and two pull-up resistors. The 74F50109 has the same pin-out and logical function as the 74F109, but the latter has a lower frequency limit and is not specified metastable-free.
The typical frequency limit of the 74F50109 is specified 150MHz. Driving the 74F50109 with a fast switching transistor 2N3960 (ft=1.6GHz) and a schottky diode 1N5712 to prevent saturation, reliable counting can be achieved up to 190-200MHz! Unlike conventional AND or OR gates, the J/K gate minimizes the jitter of the counting result (wandering of the last digit) regardless of the input signal. Since the /K input of the 74F50109 is inverted, two port pins (RA2 and RA3) of the PIC are required to drive the J and /K inputs with minimal skew.
On the other end, the counter needs to be extended beyond the 4 bits of the 74Fxxx logic and 16 bits of the TMR1 adding up to 20 bits of resolution. To avoid disrupting the operation of the main 100us timer, the TMR1 is not allowed to generate interrupts. The TMR1 overflow (interrupt) flag is checked during every 100us (TMR0)interrupt. The overflows are counted in two additional 8-bit registers. The overall counter resolution is therefore 36 bits.
These 36 bits are truncated to 32 bits, the upper 4 bits are not used. 32 bits allow counting beyond 400MHz with a resolution of 0.1Hz (gate time 10s). None of these counters is ever being reset! The counter value at the beginning of the measurement is stored and subtracted from the end value. Finally, the 32-bit binary result is converted to a 10-digit decimal number and the latter is displayed with the leading zeros blanked, decimal point and units (MHz or kHz).
The basic counter software allows three resolutions (selected with RC4 and RC5): 10Hz, 1Hz and 0.1Hz in direct counting mode (no prescaler), corresponding to gate times of 100ms, 1s and 10s. When used with a divide-by-64 prescaler, the three available resolutions become 1kHz, 100Hz and 10Hz, corresponding to gate times of 64ms, 640ms and 6.4s. All these gate times are obtained by counting the 100us (10kHz TMR0) interrupts.